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| PRELIMINARY CY26200 T1/E1 Clock Generator Features * Integrated phase-locked loop (PLL) * Low-jitter, high-accuracy outputs * 3.3V operation Part Number CY26200 Outputs 1 Input Frequency Range 19.44 MHz Benefits High-performance PLL tailored for T1/E1 clock generation Meets critical timing requirements in complex system designs Enables application compatibility Output Frequencies 1.544 MHz/2.048 MHz (selectable) Logic Block Diagram 19.44 XIN OSC XOUT Q VCO P OUTPUT DIVIDERS CLK1 PLL AVDD AVSS VDD VSS Pin Configuration CY26200 8-pin SOIC XIN AVDD FS AVSS 1 2 3 4 8 7 6 5 XOUT VSS CLK1 VDD Table 1: CY26200 Frequency Select Option Frequency Select 0 1 CLK1 1.544 2.048 Unit MHz MHz Cypress Semiconductor Corporation Document #: 38-07335 Rev. *A * 3901 North First Street * San Jose * CA 95134 * 408-943-2600 Revised December 14, 2002 PRELIMINARY Pin Summary Pin Name XIN AVDD FS AVSS VDD CLK1 VSS XOUT[1] 1 2 3 4 5 6 7 8 CY26200 Pin Number Pin Description 19.44-MHz Reference Input Analog Voltage Supply Frequency Select - see Table 1 Analog Ground Voltage Supply 1.544-MHz/2.048-MHz Clock Output Ground Reference Output Absolute Maximum Conditions Parameter VDD TS TJ Description Supply Voltage Storage Temperature[2] Junction Temperature Digital Inputs Digital Outputs Referred to VDD Electrostatic Discharge Recommended Operating Conditions Parameter VDD/AVDD TA TA CLOAD fREF tPU Description Operating Voltage Ambient Temperature (Commercial) Ambient Temperature (Industrial) Max. Load Capacitance Reference Frequency 0.05 19.44 500 VSS - 0.3 VSS - 0.3 2000 Min. 3.135 0 -40 Typ. 3.3 Max. 3.465 70 +85 15 Min. -0.5 -65 Max. 7.0 125 125 VDD + 0.3 VDD + 0.3 Unit V C C V V V Unit V C C pF MHz ms Power-up time for all VDD's to reach minimum specified voltage (power ramps must be monotonic) DC Electrical Characteristics (Commercial) Parameter IOH IOL CIN IIZ Description Output High Current Output Low Current Input Capacitance Input Leakage Current Conditions VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Min. 12 12 Typ. 24 24 Max. Unit mA mA 7 5 20 Min. 11 11 Typ. 24 24 7 5 25 Min. 45 0.8 Typ. 50 1.4 Max. 55 Max. pF A mA Unit mA mA pF A mA Unit % V/ns Supply Current Sum of Core and Output Current IDD DC Electrical Characteristics (Industrial) Parameter IOH IOL CIN IIZ Description Output High Current Output Low Current Input Capacitance Input Leakage Current Conditions VOH = VDD - 0.5, VDD = 3.3V VOL = 0.5, VDD = 3.3V Supply Current Sum of Core and Output Current IDD AC Electrical Characteristics (VDD = 3.3V, Commercial) Parameter[3] DC t3 Description Output Duty Cycle Rising Edge Slew Rate Conditions Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Notes: 1. Float XOUT if XIN is externally driven 2. Rated for 10 years 3. Not 100% tested Document #: 38-07335 Rev. *A Page 2 of 5 PRELIMINARY AC Electrical Characteristics (VDD = 3.3V, Commercial) (continued) Parameter[3] t4 t9 Description Falling Edge Slew Rate Clock Jitter Conditions Output Clock Fall Time, 80% - 20% of VDD Peak to Peak period jitter Min. 0.8 Typ. 1.4 200 CY26200 Max. Unit V/ns ps 3 ms Unit % V/ns V/ns ps 3 ms t10 PLL Lock Time AC Electrical Characteristics (VDD = 3.3V, Industrial) Parameter[3] DC t3 t4 t9 t10 Test Circuit V DD 0.1 mF OUTPUTS CLK out C LOAD Name Output Duty Cycle Rising Edge Slew Rate Falling Edge Slew Rate Clock Jitter PLL Lock Time Description Duty Cycle is defined in Figure 1, 50% of VDD Output Clock Rise Time, 20% - 80% of VDD Output Clock Fall Time, 80% - 20% of VDD Peak to Peak period jitter Min. 45 0.8 0.8 Typ. 50 1.4 1.4 200 Max. 55 GND Ordering Information Ordering Code CY26200SC CY26200SI t1 t2 CLK 50% 50% CLK Package Name S8 S8 Package Type 8-lead SOIC 8-lead SOIC Operating Range Commercial Industrial t3 80% 20% Operating Voltage 3.3V 3.3V t4 Figure 2. Rise and Fall Time Definitions Figure 1. Duty Cycle Definition; DC = t2/t1 Document #: 38-07335 Rev. *A Page 3 of 5 PRELIMINARY Package Diagram 8-lead (150-mil) SOIC S8 CY26200 51-85066-A All product and company names mentioned in this document are the trademarks of their respective holders. Document #: 38-07335 Rev. *A Page 4 of 5 (c) Cypress Semiconductor Corporation, 2002. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a Cypress Semiconductor product. Nor does it convey or imply any license under patent or other rights. Cypress Semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress Semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress Semiconductor against all charges. PRELIMINARY Document Title: CY26200 T1/E1 Clock Generator Document Number: 38-07335 REV. ** *A ECN No. 111745 121890 Issue Date 05/06/02 12/14/02 Orig. of Change CKN RBI Description of Change New Data Sheet CY26200 Power up requirements added to Operating Conditions Information Document #: 38-07335 Rev. *A Page 5 of 5 |
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